By Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page (auth.), Bart Preneel, Tsuyoshi Takagi (eds.)
This booklet constitutes the court cases of the thirteenth overseas Workshop on Cryptographic and Embedded platforms, CHES 2011, held in Nara, Japan, from September 28 till October 1, 2011.
The 32 papers provided including 1 invited speak have been conscientiously reviewed and chosen from 119 submissions. The papers are geared up in topical sections named: FPGA implementation; AES; elliptic curve cryptosystems; lattices; facet channel assaults; fault assaults; light-weight symmetric algorithms, PUFs; public-key cryptosystems; and hash functions.
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Extra resources for Cryptographic Hardware and Embedded Systems – CHES 2011: 13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings
This structure (see Figure 3) is then converted into a hard 38 T. G¨ uneysu and A. Moradi IA IB SWITCH BOX SC1 IA,1 SLICE1 SLICE2 SLICE3 SCi SC2 SCr CLK CLK IB,1 IA,2 IB,2 IA,r IB,r RNG Fig. 3. Short circuits at the input multiplexer to a logic slice (denoted by red wires) macro that can then be placed multiple times by black-box instantiation inside the FPGA conﬁguration, providing a large number of controllable SC elements. Note that modern FPGAs contain several thousands of LUTs and corresponding input multiplexers.
Before moving onto the TRNG system performance evaluation, we shall first discuss the results of our investigation on the maximum achievable resolution of the PDLs. We set up a highly accurate delay measurement system similar to the delay characterization systems presented in [9,7,6]. The circuit under test consists of four PDLs each implemented by a single 6-input LUT. The delay measurement circuit as shown in Figure 9 consists of three flip-flops: launch, sample, and capture flip-flops. At each rising edge of the clock, the launch flipflop successively sends a low-to-high and high-to-low signal through the PDLs.
9. The delay measurement circuit. The circuit under test consists of four LUTs each implementing a PDL. 005 5 10 15 x 20 25 30 (c) Delay difference Fig. 10. The measured delay of 32×32 circuit under tests containing a PDL with PDL control inputs being set to (a) A2−6 = 00000 and (b) A2−6 = 11111 respectively. The difference between the delays in these two cases is shown in (c). from 0% and reaches 100%. The center of this transition curve marks the point where the clock half period (T/2) is equal to the effective delay of the circuit under test.