By Biswajit Mishra, Bashir M. Al-Hashimi (auth.), Lars Svensson, José Monteiro (eds.)
This booklet constitutes the completely refereed post-conference lawsuits of 18th foreign Workshop on energy and Timing Modeling, Optimization and Simulation, PATMOS 2008, that includes built-in Circuit and procedure layout, held in Lisbon, Portugal in the course of September 10-12, 2008.
The 31 revised complete papers and 10 revised poster papers provided including three invited talks and four papers from a unique consultation on reconfigurable architectures have been conscientiously reviewed and chosen from various submissions. The papers are equipped in topical sections on low-leakage and subthreshold circuits, low-power equipment and types, mathematics and stories, variability and statistical timing, synchronization and interconnect, energy provides and switching noise, low-power circuits; reconfigurable architectures, circuits and strategies, strength and hold up modeling, in addition to strength optimizations addressing reconfigurable architectures.
Read or Download Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers PDF
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Extra info for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
To evaluate the eﬀectiveness of back biasing of each scheme in terms of leakage reduction, we introduce the ﬁgure of merit STOT , which is deﬁned as the back bias voltage variation needed to reduce the leakage current by a decade STOT = ∂ log ID ∂VBB −1 (2) According to its deﬁnition, lower values of STOT indicate a better suitability of the technology for leakage control through RBB. e. on the number of stacked transistors N . For this reason, STOT is evaluated in the following of this section for diﬀerent numbers of stacked transistors (see Fig.
DESSIS mixed-mode simulations were extensively performed to validate the proposed models and the theoretical results. In particular, the mirror full adder carry logic was analyzed as a case study and we observed good agreement of theoretical results with simulations. References 1. : Scaling, power, and the future of CMOS. Electron Devices Meeting. IEDM Technical Digest (2005) 2. : Demonstration analysis and device design considerations for independent DG MOSFETs. IEEE Trans. on Electron Devices 52, 2046–2053 (2005) 3.
9 nm. The FinFETs are assumed to be symmetric devices, hence both gates feature the same oxide thickness. 1 V). Table 1. Geometric parameters for the NMOS transistors. 62 nm and εox = 7 in all cases. NSD,peak : peak doping levels for source and drain. NSU B is the substrate doping, Xj is the junction depth and LS is the length of the source and drain regions. 6 VG [V] 1 (b) FinFETs Fig. 2. Simulated ID vs. 4 V as parameter. In the FinFET plot the dashed line represents the 3T (tied gates, VFG =VBG ) mode while solid lines refer to the 4T (independent gates) mode in which VG =VFG and VBG =VBB .